CBEA Note - 06

6. Memory Flow Controller

1. In a CBEA-compliant processor, the MFC serves as an interface to the system and to other elements for an SPU.
2. It provides the primary mechanism for data transfer, protection, and synchronization between main storage and the local storage arrays.
3. there is logically an MFC for each SPU in a processor.
4. MFC has two interfaces to the SPU, two interfaces to the Bus Interface Unit (BIU), and two interfaces to an optional SL1 cache.
5. SPU channel interface allows the SPU to access MFC facilities and to issue MFC commands.
6. SPU local storage interfaces is used by the MFC to access the local storage in the SPU.
7. One interface to the BIU allows memory-mapped I/O (MMIO) access to the MFC facilities. This interface also allows other processors to issue MFC
   commands. Commands issued using MMIO are referred to as MFC proxy commands.
8. The other interface to the BIU carries the real address.
9. The interfaces to the SL1 cache are mainly for data transfers.
10. One interface is used by the MFC for access to the address translation tables in main storage and the other interface of the SL1 cache is used for the transfer of data between main storage and local storage.

As shown in Figure 6-1, the following are the main units in a typical MFC:
• MMIO interface
• MFC registers
• DMA controller

1. The MMIO interface maps the MFC facilities of the SPU into the real address space of the system. (allows access to the MFC facilities from any processor, or any device in the system.)
2. MMIO interface can be configured to map the local storage of the SPU into the real address space. (map local storage to real address space)
   - allows direct access to the local storage from any processor or any device in the system
   - enabling local-store-to local-store transfers
   - ability for I/O devices to directly access the local storage domain
   
3. Coherency is not maintained between SPU and MMIO accesses of the local storage domain.

6.1 MFC Facilities

1. Most of the MFC facilities are contained in the MFC Registers unit.
2. Some facilities are contained in the Direct Memory Access Controller (DMAC).
3. The facilities within the MFC:
   User mode environment facilities include:
   • Mailbox Facility (see page 90)
   • SPU Signal Notification Facility (see page 94)
   • Proxy Tag-Group Completion Facility (see page 82)
   • MFC Multisource Synchronization Facility (see page 96)
   • SPU Control and Status Facilities (see page 86)
   • SPU Isolation Facility (see page 163)
   
   Privileged mode environment facilities include:
   • MFC Privileged Facilities (see page 197)
   – MFC State Register One (see page 197)
   – MFC Logical Partition ID Register (see page 199)
   – MFC Storage Description Register (see page 200)
   – MFC Data Address Register (see page 201)
   – MFC Data Storage Interrupt Status Register (see page 202)
   – MFC Address Compare Control Register (see page 203)
   – MFC Local Storage Address Compare Facility (see page 205)
   – MFC Command Error Register (see page 207)
   – MFC Data Storage Interrupt Pointer Register (see page 208)
   – MFC Control Register (see page 209)
   – MFC Atomic Flush Register (see page 212)
   – SPU Outbound Interrupt Mailbox Register (see page 213)
   
   • SPU Privileged Facilities (see page 215)
   – SPU Privileged Control Register (see page 215)
   – SPU Local Storage Limit Register (see page 217)
   – SPU Configuration Register (see page 221)
   • SPE Context Save and Restore (see page 223)
4. The SPEs and PPE instruct the MFC to perform these DMA operations by queuing DMA command requests to the MFC through one of the command queues:
   • Commands issued by an SPE are queued to the MFC SPU command queue
   • Commands issued by a PPE are queued to the MFC proxy command queue
5. The MFC uses a MMU to perform all MFC address translations and MFC access protection checks required for the DMA transfers.
6. The MMU handles MFC transfers in much the same way that the PPE storage addressing facility handles load-and-store operations.