CBEA Note - 05

5. Synergistic Processor Unit

1. The intent of the SPU is to fill a void between general-purpose processors and special-purpose hardware.
2. SPU aims to achieve leadership performance on critical workloads for game, media, and broadband systems.
3. The intent of the SPU and the CBEA is to provide a high degree of control to expert (real-time) programmers while maintaining ease of programming.
4. The SPU implements a new instruction set architecture (ISA).
5. The main characteristics of this architecture are:
   • Load-and-store architecture with sequential semantics, using a set of 128 registers, each of which is 128 bits wide.
   • Single-instruction, multiple-data (SIMD) capability
   – Sixteen 8-bit integers
   – Eight 16-bit integers
   – Four 32-bit integer or four single-precision floating-point values
   – Two double-precision floating point
   • Load-and-store access to an associated local storage.
   • Channel input/output for MFC control (used for external data access).
6. The SPU has the following restrictions:
   • No direct access to main storage (access to main storage using MFC facilities only)
   • No distinction between user mode and privileged state
   • No access to critical system control such as page-table entries (this restriction should be enforced by PPE privileged software).
   • No synchronization facilities for shared local storage access
7. The intent of the SPU is to enable applications that require a high computational unit density.