SH4 Notes - 03

Memory Management Unit (MMU)

Overview

• 29-bit external memory space by providing 8-bit address space identifiers
• 32-bit logical (virtual) address space
• virtual address -> MMU -> physical address
• 4 instruction TLB (ITLB) entries
• 64 unified TLB (UTLB) entries
• UTLB copies are stored in the ITLB by hardware
• SH-4 there is support for 4 page sizes: 1-kbyte, 4-kbyte, 64-kbyte and 1-Mbyte.

Register descriptions

• 6 MMU-related registers.
• Page table entry high register (PTEH) : 32 bits
  - 0xFF00 0000 (P4)
  - 0x1F00 0000 (Area 7)
  -
  
• PTEL (Page table entry low register) : 32 bits
• TTB (Translation table base register) : 32 bits
• TEA (Translation table address register) : 32 bits
• MMUCR (MMU control register) : 32 bits