SH4 Note - 01

Overview

• 32-bit RISC microprocessor
• 16-bit fixed-length instruction set
• 1 instruction cache
• 1 operand cache (copy-back/write-through, 4-entry full-associative instruction TLB)
• MMU (memory management unit) with 64-entry full-associative shared TLB.

CPU

• 32-bit internal data bus
• 32 general registers(32-bit)
  
• 8 shadow registers(32-bit)
• 7 control registers(32-bit)
• 4 system registers(32-bit)
• RISC
  
• Load-store architecture
• Delayed branch instructions
• Conditional execution
• Superscalar architecture: Parallel execution of two instructions
• C-based instruction set(providing simultaneous execution of two instructions)
  including FPU
• Instruction execution time: Maximum 2 instructions/cycle
• Virtual address space: 4 Gbytes (448-Mbyte external memory space)
• Space identifier ASIDs: 8 bits, 256 virtual address spaces
• On-chip multiplier
• Five-stage pipeline

FPU

• On-chip floating-point coprocessor
• Supports single-precision (32 bits) and double-precision (64 bits)
• IEEE754-compliant
• Two rounding modes: Round to Nearest and Round to Zero
• Floating-point registers: 32 bits x 16 words x 2 banks
  (single-precision x 16 words or double-precision x 8 words) x 2 banks
• 32-bit CPU-FPU floating-point communication register (FPUL)
• Supports FMAC (multiply-and-accumulate), FDIV (divide) and FSQRT (square root) instructions.
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• Instruction execution times:
  - Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles (double-precision)
  - Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles
  (double-precision)
  - Note: FMAC is supported for single-precision only.
• 3-D graphics instructions (single-precision only):
  - 4-dimensional vector conversion and matrix operations (FTRV): 4 cycles
  (pitch), 7 cycles (latency)
  - 4-dimensional vector (FIPR) inner product: 1 cycle (pitch), 4 cycles (latency)
• Five-stage pipeline

Power-down

• Sleep mode
• Standby mode
• Module standby function

MMU

• 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)
• Single virtual mode and multiple virtual memory mode
• Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, 1 Mbyte
• 4-entry fully-associative TLB for instructions
• 64-entry fully-associative TLB for instructions and operands
• Supports software-controlled replacement and random-counter replacement algorithm
• TLB contents can be accessed directly by address mapping