Rintarou's Notes: SH4 Note

Programming model

General registers

R0_BANK0–R7_BANK0:
- In user mode (SR.MD = 0), R0–R7 are always assigned to R0_BANK0–R7_BANK0.
- In privileged mode (SR.MD = 1), R0–R7 are assigned to R0_BANK0–R7_BANK0 only when SR.RB = 0.
Notes: SR (=Status Register). MD(=Mode)
R0_BANK1–R7_BANK1:
- In user mode, R0_BANK1–R7_BANK1 cannot be accessed.
- In privileged mode, R0–R7 are assigned to R0_BANK1–R7_BANK1 only when
SR.RB = 1.
Notes: RB (=General Register Bank specifier in privileged mode)
Programming Note:
As the user’s R0–R7 are assigned to R0_BANK0–R7_BANK0, and after an exception or interrupt R0–R7 are assigned to R0_BANK1–R7_BANK1, it is not necessary for the interrupt handler to save and restore the user’s R0–R7
(R0_BANK0–R7_BANK0).

System registers

MACH (32bit) : Multiply-and-accumulate register high
MACL (32bit) : Multiply-and-accumulate register low
PR (32bit) : Procedure register
The return address is stored when a subroutine call using a BSR, BSRF or JSR instruction. PR is referenced by the subroutine return instruction (RTS).
PC (32bit) : Program Counter
FPSCR (32bit) : Floating-point status/control register
FPUL (32bit) : Floating-point communication register
Data transfer between FPU registers and CPU registers is carried
out via the FPUL register. The FPUL register is a system register, and is accessed from the CPU side by means of LDS and STS instructions. For example, to convert the integer stored in general register R1 to a single-precision floating-point number,
the processing flow is as follows:
R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1

Control registers

SR (32bit) : Status Register
- SR.T (bit[0]) : True/False condition or carry/borrow bit.
- SR.S (bit[1]) : Specifies a saturation operation for a MAC instruction.
- SR.IMASK (bit[4:7]) : Interrupt mask level.
- SR.Q (bit[8]) : State for divide step.
- SR.M (bit[9]) : State for divide step.
- SR.FD (bit[15]) : FPU disable bit (cleared to 0 by a reset).
- SR.BL (bit[28]) : Exception/interrupt block bit
- SR.RB (bit[29]) : General register bank specifier in privileged mode
- SR.MD (bit[30]) : Processor Mode (MD=0 : User Mode, MD=1 : Privileged mode
- SR.RES (bit[[2:3],[10:14][16:27][31]) : Reserved
SSR (32bit) : Saved Status Register
The current contents of SR are saved to SSR in the event of an exception or interrupt.
SPC (32bit) : Saved Program Counter
The address of an instruction at which an interrupt or exception occurs is saved to SPC.
GBR (32bit) : Global Base Register
GBR is referenced as the base address in a GBR-referencing MOV instruction.
VBR (32bit) : Vector Base Register
VBR is referenced as the branch destination base address in the event of an exception or interrupt.
SGR (32bit) : Saved General Register
The contents of R15 are saved to SGR in the event of an exception or interrupt.
Notes: R15 被當做 Stack Pointer 來使用。(R14 則為 Base Pointer)
DBR (32bit) : Debug Base Register

Floating-point registers

Floating-point registers, FPRn_BANKi (32 registers)
Single-precision floating-point registers, FRi (16 registers)
- FPSCR.FR = 0 : FR0–FR15 are assigned to FPR0_BANK0–FPR15_BANK0.
- FPSCR.FR = 1 : FR0–FR15 are assigned to FPR0_BANK1–FPR15_BANK1.
Double-precision floating-point registers or single-precision floating-point
register pairs, DRi (8 registers):
DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7},
DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15}
Single-precision floating-point vector registers, FVi (4 registers): An FV register
comprises four FR registers:
FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7},
FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15}
Single-precision floating-point extended registers, XFi (16 registers)
- FPSCR.FR = 0 : XF0-XF15 are assigned to FPR0_BANK1-FPR15_BANK1.
- FPSCR.FR = 1 : XF0-XF15 are assigned to FPR0_BANK0-FPR15_BANK0.
Single-precision floating-point extended register pairs, XDi (8 registers): An XD
register comprises two XF registers.
XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7},
XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15}
Single-precision floating-point extended register matrix, XMTRX: XMTRX
comprises all 16 XF registers.

Notes: 太酷了！日本人的想法真的蠻好玩的。

Memory-mapped registers

The control registers are double-mapped to the following two memory areas.
All registers have two addresses.
- 0x1F00 0000-0x1FFF FFFF
- 0xFF00 0000-0xFFFF FFFF
0x1F00 0000–0x1FFF FFFF
- This area must be accessed in address translation mode using the TLB.
0xFF00 0000–0xFFFF FFFF
- Access to area 0xFF00 0000-0xFFFF FFFF in user mode will cause an address error.
- Memory-mapped registers can be referenced in user mode by means of access that involves address translation.

Data format in registers

Register operands are always longwords (32 bits). When a memory operand is only a
byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into
a register.

Data formats in memory

Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form.
A word operand must be accessed starting from a word boundary(even address of a
2-byte unit: address 2n)
A longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n).

Processor states

Reset state:
- power-on reset will cause all system components to be reset,
- manual reset may, for example, avoid resetting DRAM controllers so that
memory contents are preserved.
Exception-handling state:
- In the case of a reset, the CPU branches to address 0xA000 0000 and starts
executing the user-coded exception handling program.
- In the case of a general exception or interrupt, the program counter (PC) contents are saved in the saved program counter (SPC), the status register (SR) contents are saved in the saved status register (SSR), and the R15 contents are saved in saved general register 15 (SGR). The CPU branches to the start address of the user-coded exception service routine, found from the sum of the contents of the vector base address and the vector offset.
Program execution state:
CPU executes program instructions in sequence.
Power-down state:
The power-down state is entered by executing a SLEEP instruction.

Rintarou's Notes