CBEA Note - 03

Chapter 3. Storage Models

The CBEA-compliant processor implements two concurrent storage models for an application program:

1. virtual storage model of the PPE (also used by MFCs for DMA operations) . The PPE virtual storage model allows privileged software to provide different views of the real memory
   and I/O devices for the PPE and any MFC unit DMA transfers. It is possible for multiple virtual address spaces to exist.
   
2. local storage model of the SPU. The SPU local storage model is restricted to applications running on SPUs and data transfers handled by the MFC.

3.1 Virtual Storage Model

1. Allows applications to exist within a virtual address space larger than either the effective address space or the real address space.
2. In a typical CBEA-compliant processor system, the effective address space of each program is a subset of a larger virtual address space managed by privileged software.
3. The privileged software manages the real storage resources of the system by setting up the tables and other information used by the hardware address translation facility.
4. Access to the virtual pages can be read/write, read only, or no access.

〔
基本上記憶體管理模型還是用 segmentation 加上 paging，只是與 x86 用詞上不太一樣：

CBEA 架構下是：

             segmentation                   paging
virtual address -----------> effective address -----> real address

x86 架構下則是：

             segmentation                paging
logical address -----------> linear address -----> physical address
〕

3.2 SPU Local Storage Model

1. Each SPU has its own dedicated area of local storage.
2. The individual local storage areas can be aliased to a real address within the main storage
   domain and any PPE can access these areas by using the appropriate effective address.

3.2.1 Local Storage Access

1. The CBEA allows the local storage of an SPU to have an alias in the real address space in the main storage domain.
2. This allows other processors in the main storage domain to access local storage through appropriately mapped effective address space.

3.2.1.1 Mapping Requirements

1. Privileged software should access the aliased pages of local storage in the main storage domain.
2. If not accessed as caching inhibited, software must explicitly manage the coherency of local storage with other system caches.
   〔若不以 cache inhibited 方式來存取 local storage，就必須由程式自己來處理 cache 與真正 local storage 間同步的問題了。〕

3.2.1.2 Local Storage Access Exceptions

1. MFC commands, which access an effective address range that maps to its own local storage can produce an error or unpredictable results.
   〔 MFC command 若存取了對應到自己的 local storage 範圍時，則會產生錯誤會或不可預期的結果。因為此時 DMA 的來源與目的區塊是重疊的。〕
2. Therefore, it is the programmer's and privileged software's responsibility to avoid an unintended overlap, which can result in the corruption of data.

3.3 Single-Copy Atomicity

1. In the PowerPC Architecture, the following single register accesses are always atomic:
   • Byte accesses (all bytes are aligned on byte boundaries)
   • Halfword accesses aligned on halfword boundaries
   • Word accesses aligned on word boundaries
   • Doubleword accesses aligned on doubleword boundaries
   • Quadword accesses aligned on quadword boundaries
2. Only quadword accesses of local storage are atomic.
   〔沒有 alignment 的存取也不是 atomic 的，而在存取 local storage 時，只有 quadword access 是 atomic〕

3.4 Cache Models

1. Harvard-style cache of PPC.
   
2. A location in the data cache is considered to be modified in that cache if the location has been modified (for example, by a store instruction) and the modified data has not been written to main storage.
3. Cache management instructions allow programs to manage the caches when needed.
4. The Cache Management Instructions allow programs to:
   • Invalidate the copy of storage in an instruction cache block (icbi)
   [invalid an instruction cache]
   • Provide a hint that the program will probably soon access a specified data cache block (dcbt, dcbtst)
   [set a cache hint]
   • Set the contents of a data cache block to zeros (dcbz)
   [clear cache]
   • Copy the contents of a modified data cache block to main storage (dcbst)
   [copy back]
   • Copy the contents of a modified data cache block to main storage and make the copy of the block in the data cache invalid (dcbf)
   [copy back and set invalid]
5. The SL1 data cache commands allow programs to:
   • Bring a range of effective addresses into the SL1 (sdcrt)
   • Bring a range of effective addresses into the SL1 (sdcrtst)
   • Write zeros to the contents of a range of effective addresses (sdcrz)
   • Store the modified contents of a range of effective addresses (sdcrst)
   • Store the modified contents of a range of effective addresses and invalidate the block (sdcrf)
6. Above instructions are treated as no operations (no-op) instructions in implementations without an SL1.

3.5 Memory Coherence

1. 當一連串的存取同一個位址的 memory 時，並不能保證每次的 store 都會真的寫入到這個位址上，因為 cache 的關係，所以軟體必須要自己來控制 Memory coherence 的問題。
   (原文寫了很多，就是要說明這一點啦～)

3.6 Storage Control Attributes

1. Storage control attributes are associated with units of storage that are multiples of the page size.
   〔以 page 為單位的 storage control attributes〕
2. The storage control attributes are:
   • Write through Required
   〔從 cache 寫到了真的記憶體位址中〕
   • Caching Inhibited
   〔不使用 cache 〕
   • Memory Coherence Required
   〔需要 Memory Coherence〕
   • Guarded

3.7 Shared Storage

1. The CBEA supports the sharing of storage between programs, between different instances of the same program, between SPUs, and between processors and other devices.
2. It also supports access to a storage location by one or more programs using different effective addresses or DMA addresses.
   〔segmentation + paging 吧〕
   
3. Storage is shared in blocks of an integral number of pages.
4. When the same storage location has different effective addresses, the addresses are called aliases.
5. Each application can be granted separate access privileges to aliased pages.