CBEA Note - 04

4. PowerPC Processor Element

1. The CBEA includes a PowerPC processor, which, with the MFC is known as the PowerPC Processor Element (PPE).
2. The PPE must be a 64-bit implementation, all effective addresses and registers, except some special-purpose and memory-mapped I/O (MMIO) registers are 64 bits long.
3. All implementations have two modes of operation: 64-bit mode and 32-bit mode.
4. All instructions are available in both modes.
5. The CBEA does not permit a PPE implementation that provides only the equivalent of 32-bit mode.

4.1 PowerPC Architecture Book I and Book II Compatibility


The PPE provides binary compatibility for PowerPC applications, except as described in Section 4.1.2 Incompatibilities with PowerPC Architecture, Book I on page 39.

4.1.1 Optional Features in PowerPC Architecture, Book I (Required for CBEA)

1. The following facilities and instructions are considered optional in the PowerPC Architecture, but are required for the PPE by the CBEA user mode environment.
   • Floating reciprocal estimate single A-form (fres)
   • Floating reciprocal square-root estimate A-form (frsqte)
   • Vector/SIMD multimedia extension

4.1.2 Incompatibilities with PowerPC Architecture, Book I

1. Currently there are no incompatibilities with PowerPC Architecture, Book I.

4.1.3 Optional Features in PowerPC Architecture, Book II (Required for CBEA)

1. The following facilities and instructions are considered optional in the PowerPC Architecture, but are required in the CBEA.
   
   • Data cache block touch X-form (dcbt)
   
   This is an optional version of dcbt that permits a program to provide a hint that a sequence of data cache blocks is likely to be needed soon.
   

4.1.4 Incompatibilities with PowerPC Architecture, Book II

1. Currently there are no incompatibilities with PowerPC Architecture, Book II.

4.1.5 Extensions to the PowerPC Architecture

1. For information on extensions in the CBEA to the PowerPC Architecture, see Appendix E .